1. Field of the Invention
The present disclosure relates to non-volatile storage.
2. Description of the Related Art
Semiconductor memory has become increasingly popular for use in various electronic devices. For example, non-volatile semiconductor memory is used in cellular telephones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices and other devices. Electrically Erasable Programmable Read Only Memory (EEPROM) and flash memory are among the most popular non-volatile semiconductor memories. With flash memory, also a type of EEPROM, the contents of the whole memory array, or of a portion of the memory, can be erased in one step, in contrast to the traditional, full-featured EEPROM.
Both traditional EEPROM and flash memory utilize a floating gate that is positioned above and insulated from a channel region in a semiconductor substrate. The floating gate is positioned between the source and drain regions. A control gate is provided over and insulated from the floating gate. The threshold voltage (VTH) of the transistor thus formed is controlled by the amount of charge that is retained on the floating gate. That is, the minimum amount of voltage that must be applied to the control gate before the transistor is turned on to permit conduction between its source and drain is controlled by the level of charge on the floating gate.
Some EEPROM and flash memory devices have a floating gate that is used to store two ranges of charges and, therefore, the memory element can be programmed/erased between two states, e.g., an erased state and a programmed state. Memory cells having a threshold voltage within a first voltage range may be considered to be in the erased state and those having a threshold voltage within a second voltage range may be considered to be in the programmed state. Typically, there is a window between the first and second range. Such a flash memory device is sometimes referred to as a binary flash memory device because each memory element can store one bit of data.
A multi-state (also called multi-level) flash memory device is implemented by identifying multiple distinct allowed/valid programmed threshold voltage ranges. Each distinct threshold voltage range corresponds to a predetermined value for the set of data bits encoded in the memory device. For example, each memory element can store two bits of data when the element can be placed in one of four discrete charge bands corresponding to four distinct threshold voltage ranges.
Some flash memory devices operate as both binary and multi-states. For example, some memory cells (or groups of memory such as “blocks”) are used to store one bit of data (“single-level cell or SLC blocks”) and other memory cells are used to store multiple bits per cell (“multi-level cell or MLC blocks”). The SLC blocks may be used for short term storage of data, whereas the MLC blocks may be used for long term data storage.
For some memory arrays, the memory array is arranged as a number of parallel word lines and a number of bit lines that run perpendicular to the word lines. Each memory cell may be associated with one word line and one bit line. The memory array is oftentimes read with an operation that reads many different memory cells in unison. For example, all of the memory cells on a given word line might be read at the same time. As another alternative, every other memory cell on a given word line might be read at the same time. For example, first memory cells on a selected word line that are associated with the odd bit lines are read, then memory cells on the selected word line that are associated with the even bit lines are read.
Unfortunately, access time may be slower than desired in some cases. One possible approach to decrease access time is to read word lines ahead of time. For example, word lines are read sequentially, where reading of memory cells on the next word line in sequence is begun prior to determining that the next word line in the sequence actually contains the next data of interest. This approach can sometimes decrease access time. However, this approach might not decrease access time if the next word line does not contain data of interest. For example, if the data of interest is randomly scattered on different word lines, then reading ahead successive word lines may not be beneficial. Note that in some cases, the address of the next data that should be read is not known until after the first data is read. Therefore, reading ahead to the next word line does not necessarily save time for some data accesses, such as random data access.